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In this paper we explore the use of asynchronous routers in a time-divisionmultiplexed (TDM) network-on-chip (NOC), Argo that is being developed for a multiprocessor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either synchronous or mesochronous. We use asynchronous routers to achieve a simpler, smaller, and more robust, self-timed design. Our design exploits the fact that pipelined asynchronous circuits also behave as ripple FIFOs. Thus, it avoids the need for explicit synchronization FIFOs between the routers. Argo has interesting elastic timing properties that allow it to tolerate skew between the network interfaces (NIs). The paper presents Argo NOC-architecture and provides a quantitative analysis of its ability of absorb skew between the NIs. Using a signal transition graph model and realistic component delays derived from a 65 nm CMOS implementation, a worst case analysis shows that a typical design can tolerate a skew of 1-5 cycles (depending on FIFO depths and NI clock frequency). Simulation results of a2×2NOC confirm this. 2014 2 NVLSI1448 Topic: High Performance BIST PLL Approach for VCO Testing Abstract: RF and mixed signal IC testing is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. This paper focuses on certain mixed signal IC that is phase locked loop (PLL). A novel BIST (Built-In-SelfTest) approach is developed for RF PLL; it is particularly applied for testing the VCO block. The proposed BIST schema doesn’t break the loop to include test circuit in the PLL design stage which is achieved with minimal degradation characteristics of PLL. The key advantage of this technique is that it uses an internal test signal for evaluating the test procedure. The presented architecture uses the existing elements for measuring and testing in order to reduce the area overhead for BIST schema, solves the analog nodes loading problem and improves the test accessibility. The test output generated is a purely digital signal. The BIST method enables the detection of catastrophic and many parametric faults affected the VCO by measuring its oscillation frequency response. To evaluate the effectiveness of proposed BIST approach, a fault simulation results indicate the characteristic of the BIST structure that is RF and mixed signal IC testing is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. This paper focuses on certain mixed signal IC that is phase locked loop (PLL). A novel BIST (Built-In-SelfTest) approach is developed for RF PLL; it is particularly applied for testing the VCO block. The proposed BIST schema doesn’t break the loop to include test circuit in the PLL design stage which is achieved with minimal degradation characteristics of PLL. The key advantage of this technique is that it uses an internal test signal for evaluating the test procedure. The presented architecture uses the existing elements for measuring and testing in order to reduce the area overhead for BIST schema, solves the analog nodes loading problem and improves the test accessibility. The test output generated is a purely digital signal. The BIST method enables the detection of catastrophic and many parametric faults affected the VCO by measuring its oscillation frequency response. To evaluate the effectiveness of proposed BIST approach, a fault simulation results indicate the characteristic of the BIST structure that is high fault coverage of 100%. 2014 3 NVLSI1447 Topic: Performance Evaluation of Column-Scaled LDPC Codes Under Fading Channel Conditions Abstract: Column scaling of LDPC codes is generally done to reduce the decoding complexity without degradation in bit error rate. It has been deduced that, the so constructed CS-LDPC codes had better performance than the existing regular and deterministic LDPC in terms of Bit Error Rate (BER). In this paper, ability of Column Scaled LDPC codes in reaching the best performance is evaluated for different fading channel conditions such as Additive White Gaussian Noise (AWGN), Rayleigh and Rician channels. Diagonal elements (that are not equal to zero) are distributed randomly in order to generate CS-LDPC. In Column Scaled Low density Parity Check codes, non binary parity check matrix, H is derived using Galios field or finite field polynomial and then non-binary H matrix is converted to binary H matrix. CS-LDPC codes have parity-check matrix that are composed Column scaling of LDPC codes is generally done to reduce the decoding complexity without degradation in bit error rate. It has been deduced that, the so constructed CS-LDPC codes had better performance than the existing regular and deterministic LDPC in terms of Bit Error Rate (BER). In this paper, ability of Column Scaled LDPC codes in reaching the best performance is evaluated for different fading channel conditions such as Additive White Gaussian Noise (AWGN), Rayleigh and Rician channels. Diagonal elements (that are not equal to zero) are distributed randomly in order to generate CS-LDPC. In Column Scaled Low density Parity Check codes, non binary parity check matrix, H is derived using Galios field or finite field polynomial and then non-binary H matrix is converted to binary H matrix. CS-LDPC codes have parity-check matrix that are composed of binary and diagonal matrix that eases implementation and analysis results shows that the CS-LDPC scheme improves Bit Error Rate and Frame Error Rate for AWGN and Rician channels and no significant improvement for Rayleigh channels. 2014